| Rule Violations |
Count |
| Clearance Constraint (Gap=0.127mm) (InPolygon),(All) |
0 |
| Clearance Constraint (Gap=0.254mm) (InPoly),(InNetClass('DDR3_BYTE0') or InNetClass('DDR3_BYTE1') or InNetClass('DDR3_CTL') or InNetClass('ETH') or InNetClass('MIPI_CSI') or InNetClass('SDMCC') or InNetClass('USB 2.0')) |
0 |
| Clearance Constraint (Gap=0.102mm) (All),(InNetClass('All Nets')) |
0 |
| Clearance Constraint (Gap=0.127mm) (InPolygon),(InPolygon) |
0 |
| Clearance Constraint (Gap=0.203mm) (IsBoardOutline),(All) |
0 |
| Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
| Un-Routed Net Constraint ( (All) ) |
2 |
| Modified Polygon (Allow modified: No), (Allow shelved: No) |
0 |
| Width Constraint (Min=0.076mm) (Max=0.508mm) (Preferred=0.254mm) (All) |
0 |
| Width Constraint (Min=0.128mm) (Max=0.508mm) (Preferred=0.151mm) (InNetClass('DDR3_CTL') or InNetClass('DDR3_BYTE0') or InNetClass('DDR3_BYTE1') or InNetClass('SDMCC')) |
0 |
| Power Plane Connect Rule(Relief Connect )(Expansion=0.152mm) (Conductor Width=0.254mm) (Air Gap=0.178mm) (Entries=4) (All) |
0 |
| Hole Size Constraint (Min=0.152mm) (Max=5.08mm) (All) |
0 |
| Hole To Hole Clearance (Gap=0.254mm) (All),(All) |
0 |
| Minimum Solder Mask Sliver (Gap=0.01mm) (All),(All) |
0 |
| Silk To Solder Mask (Clearance=0.01mm) (IsPad),(All) |
0 |
| Silk to Silk (Clearance=0.01mm) (All),(All) |
0 |
| Net Antennae (Tolerance=0mm) (All) |
0 |
| Matched Lengths(Tolerance=1.016mm) (InxSignalClass('MIPI_CSI')) |
0 |
| Matched Lengths(Tolerance=2.54mm) (InxSignalClass('QSPI')) |
0 |
| Matched Lengths(Tolerance=2.794mm) (InxSignalClass('SDMCC')) |
0 |
| Matched Lengths(Tolerance=0.762mm) (InxSignalClass('DDR3_CTL')) |
0 |
| Matched Lengths(Tolerance=0.508mm) (InDifferentialPairClass('All Differential Pairs')) |
0 |
| Matched Lengths(Tolerance=0.508mm) (InxSignalClass('DDR3_BYTE0')) |
0 |
| Matched Lengths(Tolerance=0.508mm) (InxSignalClass('DDR3_BYTE1')) |
0 |
| Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) |
0 |
| Total |
2 |
