| Rule Violations |
Count |
| Clearance Constraint (Gap=0.152mm) (InPolygon),(All) |
0 |
| Clearance Constraint (Gap=0.508mm) (InPoly),(InNetClass('ETH') or InNetClass('ETH_2') or InNetClass('AHD1_CSI') or InNetClass('SDCard') or InNetClass('USB') or InNetClass('ANT') or InNetClass('ANT_GPS')) |
0 |
| Clearance Constraint (Gap=0.152mm) (All),(InNetClass('All Nets')) |
0 |
| Clearance Constraint (Gap=0.2mm) (InPolygon),(InPolygon) |
0 |
| Clearance Constraint (Gap=0.152mm) (InNet('GND_EARTH')),(InNet('GND')or InNet('VBUS')) |
0 |
| Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
| Un-Routed Net Constraint ( (All) ) |
0 |
| Modified Polygon (Allow modified: No), (Allow shelved: No) |
0 |
| Width Constraint (Min=0.076mm) (Max=0.508mm) (Preferred=0.156mm) (InNetClass('ANT') or InNetClass('ANT_GPS') or InNetClass('SDCard') or InNetClass('USIM')) |
0 |
| Width Constraint (Min=0.2mm) (Max=0.508mm) (Preferred=0.254mm) (All) |
0 |
| Power Plane Connect Rule(Relief Connect )(Expansion=0.152mm) (Conductor Width=0.25mm) (Air Gap=0.25mm) (Entries=4) (All) |
0 |
| Hole Size Constraint (Min=0.152mm) (Max=5.08mm) (All) |
0 |
| Hole To Hole Clearance (Gap=0.254mm) (All),(All) |
0 |
| Minimum Solder Mask Sliver (Gap=0.01mm) (All),(All) |
0 |
| Silk To Solder Mask (Clearance=0.01mm) (IsPad),(All) |
0 |
| Silk to Silk (Clearance=0.01mm) (All),(All) |
0 |
| Net Antennae (Tolerance=0mm) (All) |
0 |
| Matched Lengths(Tolerance=0.254mm) (InxSignalClass('xCSI')) |
0 |
| Matched Lengths(Tolerance=0.254mm) (InNetClass('ETH') or InNetClass('ETH_2')) |
0 |
| Matched Lengths(Tolerance=0.127mm) (InxSignalClass('xCSI')) |
0 |
| Matched Lengths(Tolerance=0.127mm) (InxSignalClass('SDMCC')) |
0 |
| Matched Lengths(Tolerance=0.127mm) (InNetClass('USB')) |
0 |
| Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) |
0 |
| Total |
0 |
