Design Rule Check - CamBox_RV1106_lot_1000.drc 2.7 KB

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  1. Protel Design System Design Rule Check
  2. PCB File : D:\Works\Project_Altium\CAMBOX_RV1106\CamBox_RV1106_lot_1000.PcbDoc
  3. Date : 7/20/2026
  4. Time : 3:36:19 AM
  5. Processing Rule : Clearance Constraint (Gap=0.152mm) (InPolygon),(All)
  6. Rule Violations :0
  7. Processing Rule : Clearance Constraint (Gap=0.508mm) (InPoly),(InNetClass('ETH') or InNetClass('ETH_2') or InNetClass('AHD1_CSI') or InNetClass('SDCard') or InNetClass('USB') or InNetClass('ANT') or InNetClass('ANT_GPS'))
  8. Rule Violations :0
  9. Processing Rule : Clearance Constraint (Gap=0.152mm) (All),(InNetClass('All Nets'))
  10. Rule Violations :0
  11. Processing Rule : Clearance Constraint (Gap=0.2mm) (InPolygon),(InPolygon)
  12. Rule Violations :0
  13. Processing Rule : Clearance Constraint (Gap=0.152mm) (InNet('GND_EARTH')),(InNet('GND')or InNet('VBUS'))
  14. Rule Violations :0
  15. Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
  16. Rule Violations :0
  17. Processing Rule : Un-Routed Net Constraint ( (All) )
  18. Rule Violations :0
  19. Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
  20. Rule Violations :0
  21. Processing Rule : Width Constraint (Min=0.076mm) (Max=0.508mm) (Preferred=0.156mm) (InNetClass('ANT') or InNetClass('ANT_GPS') or InNetClass('SDCard') or InNetClass('USIM'))
  22. Rule Violations :0
  23. Processing Rule : Width Constraint (Min=0.2mm) (Max=0.508mm) (Preferred=0.254mm) (All)
  24. Rule Violations :0
  25. Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.152mm) (Conductor Width=0.25mm) (Air Gap=0.25mm) (Entries=4) (All)
  26. Rule Violations :0
  27. Processing Rule : Hole Size Constraint (Min=0.152mm) (Max=5.08mm) (All)
  28. Rule Violations :0
  29. Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
  30. Rule Violations :0
  31. Processing Rule : Minimum Solder Mask Sliver (Gap=0.01mm) (All),(All)
  32. Rule Violations :0
  33. Processing Rule : Silk To Solder Mask (Clearance=0.01mm) (IsPad),(All)
  34. Rule Violations :0
  35. Processing Rule : Silk to Silk (Clearance=0.01mm) (All),(All)
  36. Rule Violations :0
  37. Processing Rule : Net Antennae (Tolerance=0mm) (All)
  38. Rule Violations :0
  39. Processing Rule : Matched Lengths(Tolerance=0.254mm) (InxSignalClass('xCSI'))
  40. Rule Violations :0
  41. Processing Rule : Matched Lengths(Tolerance=0.254mm) (InNetClass('ETH') or InNetClass('ETH_2'))
  42. Rule Violations :0
  43. Processing Rule : Matched Lengths(Tolerance=0.127mm) (InxSignalClass('xCSI'))
  44. Rule Violations :0
  45. Processing Rule : Matched Lengths(Tolerance=0.127mm) (InxSignalClass('SDMCC'))
  46. Rule Violations :0
  47. Processing Rule : Matched Lengths(Tolerance=0.127mm) (InNetClass('USB'))
  48. Rule Violations :0
  49. Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
  50. Rule Violations :0
  51. Violations Detected : 0
  52. Waived Violations : 0
  53. Time Elapsed : 00:00:03