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Design Rule Check - SOM_RV1106.drc

Design Rule Check - SOM_RV1106.drc 3.1 KB
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  1. Protel Design System Design Rule Check
    2. 

  2. PCB File : E:\HARDWARE\GitDVD\AITHINGS_SOM_RV1106\SOM_RV1106.PcbDoc
    3. 

  3. Date     : 20/07/2026
    4. 

  4. Time     : 2:49:01 CH
    5. 

  5. 

  6. Processing Rule : Clearance Constraint (Gap=0.127mm) (InPolygon),(All)
    7. 

  7. Rule Violations :0
    8. 

  8. 

  9. Processing Rule : Clearance Constraint (Gap=0.254mm) (InPoly),(InNetClass('DDR3_BYTE0') or InNetClass('DDR3_BYTE1') or InNetClass('DDR3_CTL') or InNetClass('ETH') or InNetClass('MIPI_CSI') or InNetClass('SDMCC') or InNetClass('USB 2.0'))
    10. 

  10. Rule Violations :0
    11. 

  11. 

  12. Processing Rule : Clearance Constraint (Gap=0.102mm) (All),(InNetClass('All Nets'))
    13. 

  13. Rule Violations :0
    14. 

  14. 

  15. Processing Rule : Clearance Constraint (Gap=0.127mm) (InPolygon),(InPolygon)
    16. 

  16. Rule Violations :0
    17. 

  17. 

  18. Processing Rule : Clearance Constraint (Gap=0.203mm) (IsBoardOutline),(All)
    19. 

  19. Rule Violations :0
    20. 

  20. 

  21. Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
    22. 

  22. Rule Violations :0
    23. 

  23. 

  24. Processing Rule : Un-Routed Net Constraint ( (All) )
    25. 

  25.    Violation between Un-Routed Net Constraint: Region (0 hole(s)) L1 (Sign) Dead Copper - Net Not Assigned.
    26. 

  26.    Violation between Un-Routed Net Constraint: Region (0 hole(s)) L4 (Sign) Dead Copper - Net Not Assigned.
    27. 

  27. Rule Violations :2
    28. 

  28. 

  29. Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
    30. 

  30. Rule Violations :0
    31. 

  31. 

  32. Processing Rule : Width Constraint (Min=0.076mm) (Max=0.508mm) (Preferred=0.254mm) (All)
    33. 

  33. Rule Violations :0
    34. 

  34. 

  35. Processing Rule : Width Constraint (Min=0.128mm) (Max=0.508mm) (Preferred=0.151mm) (InNetClass('DDR3_CTL') or InNetClass('DDR3_BYTE0') or InNetClass('DDR3_BYTE1') or InNetClass('SDMCC'))
    36. 

  36. Rule Violations :0
    37. 

  37. 

  38. Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.152mm) (Conductor Width=0.254mm) (Air Gap=0.178mm) (Entries=4) (All)
    39. 

  39. Rule Violations :0
    40. 

  40. 

  41. Processing Rule : Hole Size Constraint (Min=0.152mm) (Max=5.08mm) (All)
    42. 

  42. Rule Violations :0
    43. 

  43. 

  44. Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
    45. 

  45. Rule Violations :0
    46. 

  46. 

  47. Processing Rule : Minimum Solder Mask Sliver (Gap=0.01mm) (All),(All)
    48. 

  48. Rule Violations :0
    49. 

  49. 

  50. Processing Rule : Silk To Solder Mask (Clearance=0.01mm) (IsPad),(All)
    51. 

  51. Rule Violations :0
    52. 

  52. 

  53. Processing Rule : Silk to Silk (Clearance=0.01mm) (All),(All)
    54. 

  54. Rule Violations :0
    55. 

  55. 

  56. Processing Rule : Net Antennae (Tolerance=0mm) (All)
    57. 

  57. Rule Violations :0
    58. 

  58. 

  59. Processing Rule : Matched Lengths(Tolerance=1.016mm) (InxSignalClass('MIPI_CSI'))
    60. 

  60. Rule Violations :0
    61. 

  61. 

  62. Processing Rule : Matched Lengths(Tolerance=2.54mm) (InxSignalClass('QSPI'))
    63. 

  63. Rule Violations :0
    64. 

  64. 

  65. Processing Rule : Matched Lengths(Tolerance=2.794mm) (InxSignalClass('SDMCC'))
    66. 

  66. Rule Violations :0
    67. 

  67. 

  68. Processing Rule : Matched Lengths(Tolerance=0.762mm) (InxSignalClass('DDR3_CTL'))
    69. 

  69. Rule Violations :0
    70. 

  70. 

  71. Processing Rule : Matched Lengths(Tolerance=0.508mm) (InDifferentialPairClass('All Differential Pairs'))
    72. 

  72. Rule Violations :0
    73. 

  73. 

  74. Processing Rule : Matched Lengths(Tolerance=0.508mm) (InxSignalClass('DDR3_BYTE0'))
    75. 

  75. Rule Violations :0
    76. 

  76. 

  77. Processing Rule : Matched Lengths(Tolerance=0.508mm) (InxSignalClass('DDR3_BYTE1'))
    78. 

  78. Rule Violations :0
    79. 

  79. 

  80. Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
    81. 

  81. Rule Violations :0
    82. 

  82. 

  83. 

  84. Violations Detected : 2
    85. 

  85. Waived Violations : 0
    86. 

  86. Time Elapsed        : 00:00:01
    87.