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- Protel Design System Design Rule Check
- PCB File : E:\HARDWARE\GitDVD\AITHINGS_SOM_RV1106\SOM_RV1106.PcbDoc
- Date : 20/07/2026
- Time : 2:49:01 CH
- Processing Rule : Clearance Constraint (Gap=0.127mm) (InPolygon),(All)
- Rule Violations :0
- Processing Rule : Clearance Constraint (Gap=0.254mm) (InPoly),(InNetClass('DDR3_BYTE0') or InNetClass('DDR3_BYTE1') or InNetClass('DDR3_CTL') or InNetClass('ETH') or InNetClass('MIPI_CSI') or InNetClass('SDMCC') or InNetClass('USB 2.0'))
- Rule Violations :0
- Processing Rule : Clearance Constraint (Gap=0.102mm) (All),(InNetClass('All Nets'))
- Rule Violations :0
- Processing Rule : Clearance Constraint (Gap=0.127mm) (InPolygon),(InPolygon)
- Rule Violations :0
- Processing Rule : Clearance Constraint (Gap=0.203mm) (IsBoardOutline),(All)
- Rule Violations :0
- Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
- Rule Violations :0
- Processing Rule : Un-Routed Net Constraint ( (All) )
- Violation between Un-Routed Net Constraint: Region (0 hole(s)) L1 (Sign) Dead Copper - Net Not Assigned.
- Violation between Un-Routed Net Constraint: Region (0 hole(s)) L4 (Sign) Dead Copper - Net Not Assigned.
- Rule Violations :2
- Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
- Rule Violations :0
- Processing Rule : Width Constraint (Min=0.076mm) (Max=0.508mm) (Preferred=0.254mm) (All)
- Rule Violations :0
- Processing Rule : Width Constraint (Min=0.128mm) (Max=0.508mm) (Preferred=0.151mm) (InNetClass('DDR3_CTL') or InNetClass('DDR3_BYTE0') or InNetClass('DDR3_BYTE1') or InNetClass('SDMCC'))
- Rule Violations :0
- Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.152mm) (Conductor Width=0.254mm) (Air Gap=0.178mm) (Entries=4) (All)
- Rule Violations :0
- Processing Rule : Hole Size Constraint (Min=0.152mm) (Max=5.08mm) (All)
- Rule Violations :0
- Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
- Rule Violations :0
- Processing Rule : Minimum Solder Mask Sliver (Gap=0.01mm) (All),(All)
- Rule Violations :0
- Processing Rule : Silk To Solder Mask (Clearance=0.01mm) (IsPad),(All)
- Rule Violations :0
- Processing Rule : Silk to Silk (Clearance=0.01mm) (All),(All)
- Rule Violations :0
- Processing Rule : Net Antennae (Tolerance=0mm) (All)
- Rule Violations :0
- Processing Rule : Matched Lengths(Tolerance=1.016mm) (InxSignalClass('MIPI_CSI'))
- Rule Violations :0
- Processing Rule : Matched Lengths(Tolerance=2.54mm) (InxSignalClass('QSPI'))
- Rule Violations :0
- Processing Rule : Matched Lengths(Tolerance=2.794mm) (InxSignalClass('SDMCC'))
- Rule Violations :0
- Processing Rule : Matched Lengths(Tolerance=0.762mm) (InxSignalClass('DDR3_CTL'))
- Rule Violations :0
- Processing Rule : Matched Lengths(Tolerance=0.508mm) (InDifferentialPairClass('All Differential Pairs'))
- Rule Violations :0
- Processing Rule : Matched Lengths(Tolerance=0.508mm) (InxSignalClass('DDR3_BYTE0'))
- Rule Violations :0
- Processing Rule : Matched Lengths(Tolerance=0.508mm) (InxSignalClass('DDR3_BYTE1'))
- Rule Violations :0
- Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
- Rule Violations :0
- Violations Detected : 2
- Waived Violations : 0
- Time Elapsed : 00:00:01
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